With addition of decision feedback equalization to memory devices, such as but not limited to double data rate fourth-generation dynamic random-access memory (DDR4) and double data rate fifth-generation dynamic random-access memory (DDR5), as well as other future products, efficient ways to characterize the decision feedback equalization circuitry integrated into these devices would enhance the applicability of these devices. A decision feedback equalizer (DFE) can include taps that tap the output signal of the DFE and provide feedback to the input such that a weighted sum of the tapped signals can be subtracted from the input signal. Tap can refer to a weighted signal fed back, where the weight can also be referred to as tap coefficient.
Typically, testing of a DFE can be performed by optimizing its taps to zero out inter-symbol interference (ISI) in a golden channel. A golden channel is a transmission channel created with known amounts of degradation. The golden channel can be used to predict which DFE settings can be implemented to cancel out that degradation, where demonstrating that the degradation can be cancelled shows that the DFE is working. This process, using a golden channel, would indicate DFE functionality, but it would not be sufficient to highlight characteristics of the taps of the DFE tested.